View 74AHC573D_3252715.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the 74ahc573; 74ahct573 is a high-speed si-g ate cmos device and is pin compatible with low-power schottky ttl (lsttl). it is s pecified in compliance with jedec standard no. 7a. the 74ahc573; 74ahct573 consists of eigh t d-type transparent latches featuring separate d-type inputs for each latch and 3-state true outputs for bus oriented applications. a latch enable input (le) and an output enable input (oe ) are common to all latches. when pin le is high, data at the dn inputs enters the latches. in this condition the latches are transparent, i.e. a latch output will change state ea ch time its corresponding dn input changes. when pin le is low, the la tches store the information that is present at the dn inputs, after a set-up time pr eceding the high-to-low transition of le. when pin oe is low, the contents of the 8 latches are available at the outputs. when pin oe is high, the outputs go to the high-impedance off-state. operation of the oe input does not affect the state of the latches. the 74ahc573; 74ahct573 is functionally identical to the 74ahc373; 74ahct373, but has a different pin arrangement. 2. features and benefits ? balanced propagation delays ? all inputs have a schmitt trigger action ? common 3-state output enable input ? functionally identical to the 74ahc373; 74ahct373 ? inputs accept voltages higher than v cc ? input levels: ? for 74ahc573: cmos input level ? for 74ahct573: ttl input level ? esd protection: ? hbm eia/jesd22-a114e exceeds 2000 v ? mm eia/jesd22-a1 15-a exceeds 200 v ? cdm eia/jesd22-c101c exceeds 1000 v ? multiple package options ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c 74ahc573; 74ahct573 octal d-type transparant latch; 3-state rev. 6 ? 25 november 2010 product data sheet
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 2 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74ahc573 74AHC573D ? 40 ? c to +125 ? c so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 74ahc573pw ? 40 ? c to +125 ? c tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 74ahc573bq ? 40 ? c to +125 ? c dhvqfn20 plastic dual in-line compatible thermal enhanced very thin quad flat package no leads; 20 terminals; body 2.5 ? 4.5 ? 0.85 mm sot764-1 74ahct573 74ahct573d ? 40 ? c to +125 ? c so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 74ahct573pw ? 40 ? c to +125 ? c tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 74ahct573bq ? 40 ? c to +125 ? c dhvqfn20 plastic dual in-line compatible thermal enhanced very thin quad flat package no leads; 20 terminals; body 2.5 ? 4.5 ? 0.85 mm sot764-1 fig 1. functional diagram mna809 3-state outputs latch 1 to 8 q0 q1 q2 q3 q4 q5 q6 q7 12 13 14 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 le oe 9 11 1 8 7 6 5 4 3 2
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 3 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state fig 2. logic symbol fig 3. iec logic symbol mna807 d0 d1 d2 d3 d4 d5 d6 d7 le oe q0 q1 q2 q3 q4 q5 q6 q7 1 11 12 13 14 15 16 17 18 19 9 8 7 6 5 4 3 2 mna808 12 13 14 15 16 17 18 11 c1 1 en1 1d 19 9 8 7 6 5 4 3 2 fig 4. logic diagram mna810 q4 d4 d le q q3 d3 d le q q2 d2 d le q q1 d1 d le lele q q0 d0 d latch 1 latch 2 latch 3 latch 4 latch 5 q le oe le le le le q5 d5 d le q latch 6 le q6 d6 d le q latch 7 le q7 d7 d le q latch 8 le
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 4 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state 5. pinning information 5.1 pinning 5.2 pin description (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 5. pin configuration so20 and tssop20 fig 6. pin configuration dhvqfn20 573 oe v cc d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 gnd le 001aad099 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 001aal532 74ahc573 74ahct573 transparent top view q7 d6 d7 q6 d5 q5 d4 q4 d3 q3 d2 q2 d1 q1 d0 q0 gnd le oe v cc 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 10 11 1 20 terminal 1 index area gnd (1) table 2. pin description symbol pin description oe 1 output enable input (active low) d0 to d7 2, 3, 4, 5, 6, 7, 8, 9 data input gnd 10 ground (0 v) le 11 latch enable (active high) q0 to q7 19, 18, 17, 16, 15, 14, 13, 12 data output v cc 20 supply voltage
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 5 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state 6. functional description [1] h = high voltage level; h = high voltage level one set-up time prior to the high-to-low le transition; l = low voltage level; l = low voltage level one set-up time prior to the high-to-low le transition; z = high-impedance off-state. 7. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] for so20 packages: above 70 ? c the value of p tot derates linearly at 8 mw/k. for tssop20 packages: above 60 ? c the value of p tot derates linearly at 5.5 mw/k. for dhvqfn20 packages: above 60 ? c the value of p tot derates linearly with 4.5 mw/k. table 3. function table [1] operating mode input internal latch output oe le dn qn enable and read register (transparent mode) lhll l hh h latch and read register l l l l l hh h latch register and disable outputs h l l l z hh z table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +7.0 v v i input voltage ? 0.5 +7.0 v i ik input clamping current v i < ? 0.5 v [1] ? 20 - ma i ok output clamping current v o < ? 0.5 v or v o >v cc +0.5v [1] ? 20 +20 ma i o output current v o = ? 0.5 v to (v cc +0.5v) ? 25 +25 ma i cc supply current - +75 ma i gnd ground current ? 75 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = ? 40 ? c to +125 ?c [2] - 500 mw
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 6 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state 8. recommended operating conditions 9. static characteristics table 5. operating conditions symbol parameter conditions min typ max unit 74ahc573 v cc supply voltage 2.0 5.0 5.5 v v i input voltage 0 - 5.5 v v o output voltage 0 - v cc v t amb ambient temperature ? 40 +25 +125 ?c ? t/ ? v input transition rise and fall rate v cc = 3.0 v to 3.6 v - - 100 ns/v v cc = 4.5 v to 5.5 v - - 20 ns/v 74ahct573 v cc supply voltage 4.5 5.0 5.5 v v i input voltage 0 - 5.5 v v o output voltage 0 - v cc v t amb ambient temperature ? 40 +25 +125 ?c ? t/ ? v input transition rise and fall rate v cc = 4.5 v to 5.5 v - - 20 ns/v table 6. static characteristics at recommended operating conditions; voltag es are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ max min max min typ max 74ahc573 v ih high-level input voltage v cc = 2.0 v 1.5 - - 1.5 - 1.5 - - v v cc = 3.0 v 2.1 - - 2.1 - 2.1 - - v v cc = 5.5 v 3.85 - - 3.85 - 3.85 - - v v il low-level input voltage v cc = 2.0 v - - 0.5 - 0.5 - - 0.5 v v cc = 3.0 v - - 0.9 - 0.9 - - 0.9 v v cc = 5.5 v - - 1.65 - 1.65 - - 1.65 v v oh high-level output voltage v i = v ih or v il i o = ? 50 ? a; v cc = 2.0 v 1.9 2.0 - 1.9 - 1.9 - - v i o = ? 50 ? a; v cc = 3.0 v 2.9 3.0 - 2.9 - 2.9 - - v i o = ? 50 ? a; v cc = 4.5 v 4.4 4.5 - 4.4 - 4.4 - - v i o = ? 4.0 ma; v cc = 3.0 v 2.58 - - 2.48 - 2.40 - - v i o = ? 8.0 ma; v cc = 4.5 v 3.94 - - 3.80 - 3.70 - - v v ol low-level output voltage v i = v ih or v il i o = 50 ? a; v cc = 2.0 v - 0 0.1 - 0.1 - - 0.1 v i o = 50 ? a; v cc = 3.0 v - 0 0.1 - 0.1 - - 0.1 v i o = 50 ? a; v cc = 4.5 v - 0 0.1 - 0.1 - - 0.1 v i o = 4.0 ma; v cc = 3.0 v - - 0.36 - 0.44 - - 0.55 v i o = 8.0 ma; v cc = 4.5 v - - 0.36 - 0.44 - - 0.55 v
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 7 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state i oz off-state output current v i =v ih or v il ; v o =v cc or gnd; v cc =5.5v -- ? 0.25 - ? 2.5 - - ? 10.0 ? a i i input leakage current v i =v cc or gnd; v cc =0vto 5.5v - - 0.1 - 1.0 - - 2.0 ? a i cc supply current v i =v cc or gnd; i o =0a; v cc =5.5v - - 4.0 - 40 - - 80 ? a c i input capacitance v i =v cc or gnd - 3 10 - 10 - - 10 pf c o output capacitance -4- - - - -10pf 74ahct573 v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 - - 2.0 - 2.0 - - v v il low-level input voltage v cc = 4.5 v to 5.5 v - - 0.8 - 0.8 - - 0.8 v v oh high-level output voltage v i = v ih or v il ; v cc = 4.5 v i o = ? 50 ? a 4.4 4.5 - 4.4 - 4.4 - - v i o = ? 8.0 ma 3.94 - - 3.80 - 3.70 - - v v ol low-level output voltage v i = v ih or v il ; v cc = 4.5 v i o = 50 ? a-00.1-0.1--0.1v i o = 8.0 ma - - 0.36 - 0.44 - - 0.55 v i oz off-state output current v i =v ih or v il ; v o =v cc or gnd per input pin; other inputs at v cc or gnd; i o =0 a -- ? 0.25 - ? 2.5 - - ? 10.0 ? a i i input leakage current v i = 5.5 v or gnd; v cc =0vto 5.5v - - 0.1 - 1.0 - - 2.0 ? a i cc supply current v i =v cc or gnd; i o = 0 a; v cc =5.5v - - 4.0 - 40 - - 80 ? a ? i cc additional supply current per input pin; v i =v cc ? 2.1 v; i o =0 a; other pins at v cc or gnd; v cc = 4.5 v to 5.5 v - - 1.35 - 1.5 - - 1.5 ma c i input capacitance v i =v cc or gnd - 3 10 - 10 - - 10 pf c o output capacitance -4- - - - -10pf table 6. static characteristics ?continued at recommended operating conditions; voltag es are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ max min max min typ max
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 8 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state 10. dynamic characteristics table 7. dynamic characteristics voltages are referenced to gnd (ground = 0 v); for test circuit see figure 11 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max min max 74ahc573 t pd propagation delay dn to qn; see figure 7 [2] v cc = 3.0 v to 3.6 v c l = 15 pf - 5.5 11.0 1.0 13.0 1.0 14.0 ns c l = 50 pf - 7.8 14.5 1.0 16.5 1.0 18.5 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 3.9 6.8 1.0 8.0 1.0 8.5 ns c l = 50 pf - 5.5 8.8 1.0 10.0 1.0 11.0 ns le to qn; see figure 8 [2] v cc = 3.0 v to 3.6 v c l = 15 pf - 5.8 11.9 1.0 14.0 1.0 15.0 ns c l = 50 pf - 8.3 15.4 1.0 17.5 1.0 19.5 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 4.2 7.7 1.0 9.0 1.0 10.0 ns c l = 50 pf - 5.9 9.7 1.0 11.0 1.0 12.5 ns t en enable time oe to qn; see figure 9 [3] v cc = 3.0 v to 3.6 v c l = 15 pf - 5.8 11.5 1.0 13.5 1.0 14.5 ns c l = 50 pf - 8.3 15.0 1.0 17.0 1.0 19.0 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 4.4 7.7 1.0 9.0 1.0 10.0 ns c l = 50 pf - 6.3 9.7 1.0 11.0 1.0 12.5 ns t dis disable time oe to qn; see figure 9 [4] v cc = 3.0 v to 3.6 v c l = 15 pf - 6.8 11.0 1.0 13.0 1.0 14.0 ns c l = 50 pf - 9.7 14.5 1.0 16.5 1.0 18.5 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 4.6 7.7 1.0 9.0 1.0 10.0 ns c l = 50 pf - 7.4 9.7 1.0 11.0 1.0 12.5 ns t w pulse width le high; see figure 8 v cc = 3.0 v to 3.6 v 5.0 - - 5.0 - 5.0 - ns v cc = 4.5 v to 5.5 v 5.0 - - 5.0 - 5.0 - ns t su set-up time dn to le; see figure 10 v cc = 3.0 v to 3.6 v 3.5 - - 3.5 - 3.5 - ns v cc = 4.5 v to 5.5 v 3.5 - - 3.5 - 3.5 - ns
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 9 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state [1] typical values are measured at nominal supply voltage (v cc = 3.3 v and v cc = 5.0 v). [2] t pd is the same as t phl and t plh . [3] t en is the same as t pzh and t pzl . [4] t dis is the same as t phz and t plz . [5] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l ? v cc 2 ? f o ) = sum of the outputs. t h hold time dn to le; see figure 10 v cc = 3.0 v to 3.6 v 1.5 - - 1.5 - 1.5 - ns v cc = 4.5 v to 5.5 v 1.5 - - 1.5 - 1.5 - ns c pd power dissipation capacitance f i = 1 mhz; v i =gndtov cc [5] -12- - - - -pf 74ahct573; v cc = 4.5 v to 5.5 v t pd propagation delay dn to qn; see figure 7 [2] c l = 15 pf - 3.5 5.5 1 6.5 1 7.0 ns c l = 50 pf - 4.9 7.5 1 8.5 1 9.5 ns le to qn; see figure 8 [2] c l = 15 pf - 3.9 6.0 1 7.0 1 7.5 ns c l = 50 pf - 5.5 8.5 1 9.5 1 11.0 ns t en enable time oe to qn; see figure 9 [3] c l = 15 pf - 4.1 6.5 1 7.5 1 8.5 ns c l = 50 pf - 5.9 8.5 1 10.0 1 11.0 ns t dis disable time oe to qn; see figure 9 [4] c l = 15 pf - 4.5 6.5 1 7.5 1 8.5 ns c l = 50 pf - 6.4 9.0 1 10.0 1 11.5 ns t w pulse width le high; see figure 8 5.0 - - 5.0 - 5.0 - ns t su set-up time dn to le; see figure 10 3.5 - - 3.5 - 3.5 - ns t h hold time dn to le; see figure 10 1.5 - - 1.5 - 1.5 - ns c pd power dissipation capacitance f i = 1 mhz; v i =gndtov cc [5] -18- - - - -pf table 7. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v); for test circuit see figure 11 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max min max
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 10 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state 11. waveforms measurement points are given in table 8 . v ol and v oh are typical voltage output levels that occur with the output load. fig 7. data input to output propagation delays mna811 dn input qn output t phl t plh gnd v i v m v m v oh v ol v ol and v oh are typical voltage output levels that occur with the output load. fig 8. latch enable input to output propagation delays mna812 le input qn output t phl t plh t w 1/f max v m v oh v i gnd v ol v m
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 11 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state measurement points are given in table 8 . v ol and v oh are typical voltage output levels that occur with the output load. fig 9. enable and disable times mna813 t plz t phz outputs disabled outputs enabled v y v x outputs enabled qn output low-to-off off-to-low qn output high-to-off off-to-high oe input v ol v oh v cc v i v m gnd gnd t pzl t pzh v m v m measurement points are given in table 8 . v ol and v oh are typical voltage output levels that occur with the output load. the shaded areas indicate when the input is permi tted to change for predicable output performance. fig 10. data set-up and hold times mna814 t h t su t h t su v m v m v i gnd v i gnd le input dn input table 8. measurement points type input output v m v m v x v y 74ahc573 0.5 ? v cc 0.5 ? v cc v ol + 0.3 v v oh ? 0.3 v 74ahct573 1.5 v 0.5 ? v cc v ol + 0.3 v v oh ? 0.3 v
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 12 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state test data is given in table 9 . definitions test circuit: r t = termination resistance should be equal to output impedance z o of the pulse generator. c l = load capacitance including jig and probe capacitance. r l = load resistance. s1 = test selection switch. fig 11. test circuitry for switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aad983 dut v cc v cc v i v o r t r l s1 c l open g table 9. test data type input load s1 position v i t r , t f c l r l t phl , t plh t pzh , t phz t pzl , t plz 74ahc573 v cc ? 3.0ns 15pf, 50pf 1k ? open gnd v cc 74ahct573 3.0 v ? 3.0ns 15pf, 50pf 1k ? open gnd v cc
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 13 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state 12. package outline fig 12. package outline sot163-1 (so20) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z ywv references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 99-12-27 03-02-19
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 14 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state fig 13. package outline sot360-1 (tssop20) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 11 0 20 11 pin 1 index tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 15 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state fig 14. package outline sot764-1 (dhvqfn20) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 4.6 4.4 d h 3.15 2.85 y 1 2.6 2.4 1.15 0.85 e 1 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot764-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot764-1 dhvqfn20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 29 19 12 11 10 1 20 x d e c b a terminal 1 index area ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 16 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state 13. abbreviations 14. revision history table 10. abbreviations acronym description cdm charged device model cmos complementary metal-oxide semiconductor esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice supersedes 74ahc_ahct573 v.6 20101125 product data sheet - 74ahc_ahct573 v.5 modifications: ? figure note [1] of figure 6 : added. 74ahc_ahct573 v.5 20100325 product data sheet - 74ahc_ahct573 v.4 74ahc_ahct573 v.4 20100303 product data sheet - 74ahc_ahct573 v.3 74ahc_ahct573 v.3 20080424 product data sheet - 74ahc_ahct573 v.2 74ahc_ahct573 v.2 20031208 product specification - 74ahc_ahct573 v.1 74ahc_ahct573 v.1 19990927 product specification - -
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 17 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qua lified for use in automotive applications. the product is not desi gned, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be ex pected to result in personal injury, death or severe property or environmental dam age. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74ahc_ahct573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 6 ? 25 november 2010 18 of 19 nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from national authorities. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74ahc573; 74ahct573 octal d-type transparant latch; 3-state ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 25 november 2010 document identifier: 74ahc_ahct573 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 5 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 recommended operating conditions. . . . . . . . 6 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 17 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16 contact information. . . . . . . . . . . . . . . . . . . . . 18 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

▲Up To Search▲

Price & Availability of 74AHC573D

	To Download 74AHC573D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .